AI chips will be used in robots, smart homes, and autonomous vehicles, all of which could have an impact on the economy. 

The LLM revolution has caused a huge spike in the need for AI-capable central processing units. To boost the performance of deep learning applications in the cloud, Amazon Web Services (AWS) developed a custom machine learning inference chip they dubbed AWS Inferentia. Also, the Colossus MK2 IPU processor was developed in concert with the Poplar SDK to speed up AI. It is a novel type of massively parallel CPU.

IBM Research has made a new AI chip to help with deep learning reasoning.

Many people have been interested in trying to rethink how AI works on a computational level. Analog in-memory computing, or just "analog AI," might be able to solve the problem at hand because it is based on how neural networks work in real brains. 

In this case, the "weights" are the strengths of synapses, which control how strongly neurons in our brains and the brains of many other animals connect. 

Analog AI implementation

Implementing analog AI requires overcoming two significant obstacles: These data stores must be able to do computations with the same accuracy as current digital systems and interact naturally with the analog AI chip's other digital compute units and digital communication fabric.

IBM Research published a study introducing cutting-edge mixed-signal analog AI hardware capable of conducting a wide range of workloads, marking a significant step towards resolving these issues. It's the first time an analog chip is equally effective at computer vision AI tasks as its digital counterparts while being significantly more efficient in power consumption.

Analogue in-memory computing

The study explains how AI computing energy costs can be decreased by using Analogue in-memory computing (AIMC). By doing computations directly within memory, the latency and energy consumption of deep neural network inference tasks could be decreased by employing analog in-memory computing (AIMC) with resistive memory devices. However, AIMC must be paired with on-chip digital processes and on-chip communication to improve latency and energy usage.

Computations

According to the study, the group successfully designed and constructed a multicore AIMC chip using backend-integrated phase-change memory and 14 nm complementary metal-oxide-semiconductor technology. The chip's 64 AIMC cores are connected by an on-chip communication network, making it a fully integrated device. Individual convolutional layers and lengthy short-term memory units have their digital activation functions and other processing implemented. All the computations related to the weight layers and the activation functions are implemented on the chip, allowing us to show near software-equivalent inference accuracy with ResNet and extended short-term memory networks.

Multicore AIMC chip

The chip was made at IBM's Albany NanoTech Complex. It is made up of 64 analog in-memory compute cores or tiles. Each tile has a 256-by-256 crossbar grid of synaptic unit cells. Each tile has a small, time-based analog-to-digital translator built in to move between the analog and digital worlds. Each tile also has small digital processing units built in. These units do simple nonlinear neural activation functions and scaling operations. On the CIFAR-10 picture dataset, IBM's researchers used the chip to achieve a precision of 92.81%, making it the subject of the most extensive investigation of the computing accuracy of analog in-memory computing to date. 

Conclusion

The researchers demonstrated in the paper how to mix analog in-memory computing with several digital processor units and a digital communication network without any noticeable performance degradation. While maintaining the same energy efficiency, the chip's reported throughput per area for 8-bit input-output matrix multiplications of 400 GOPS/mm2 is more than 15 times higher than earlier multicore, in-memory computing chips based on resistive memory.

Furthermore, when combined with the sophisticated hardware-aware training they've built in recent years, IBM predicts that these accelerators will enable neural network accuracies on par with those achieved in software for a wide range of models.

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