IISc researchers have created a design framework for the creation of next-generation analog computing chipsets, which may operate quicker and with less power than the digital chips used in most electronic gadgets.

The team created a prototype of an analog chipset named ARYABHAT-1 (Analog Reconfigurable Technology and Bias-scalable Hardware for AI Tasks) using their innovative design methodology, according to a release from the Bengaluru-based IISc.

ARYABHAT-1, or the Analog Reconfigurable Technology and Bias-scalable Hardware for AI Tasks, is particularly useful for AI-based applications dealing with object or speech recognition systems, such as Alexa and Siri. Additionally, they are incredibly effective for operations requiring enormous parallel computing at high rates.

Image source: ARYABHAT-1 Chip Micrograph. Credits: NeuRonICS Lab, DESE, IISc

Most computing equipment, including mobile phones, laptops, and desktop computers, utilize digital chips due to the simplicity and scalability of the design process. However, Chetak Singh Thakur, an assistant professor in the Department of Electronic Systems Engineering (DESE) at IISc, says, "The advantage of analogue is enormous. There will be a significant increase in both power and size. In addition, analogue computing may beat digital computing in applications that do not require accurate computations since it is more energy-efficient.

Image source: NeuRonICS Lab, DESE, IISc

According to the researchers, ARYABHAT operates stably across an extensive temperature range with various machine learning architectures, like other digital computers. In addition, the architecture is "bias-scalable," meaning that its performance is unaffected by varying operating circumstances such as voltage or current. This bias-scalable implies that we can configure the same chipset for ultra-efficient Internet of Things (IoT) applications and high-speed operations such as object detection.

Energy-efficiency

Despite this, numerous technical obstacles exist to overcome while creating analog chips. Analog processors are more challenging to test and co-design than digital circuits. Compiling a high-level code facilitates the synthesis of large-scale digital processors. The same design may be ported across successive generations of technology advancement – for example, from a 7 nm chipset to a 3 nm chipset – with minimum adjustments. Due to the inability of analog chips to scale – they must be individually modified when transferring to the next generation of technology or a new application – their design is costly.

Balancing precision and speed against power and area is challenging regarding analogue design. In digital design, we can increase precision by adding more components, such as logic units, to the same chip. In addition, we can alter their operating power without compromising device performance.

To overcome these obstacles, the team has created a novel framework that permits building analog processors that scale similarly to digital processors. In addition, their chipset is reconfigurable and programmable, allowing identical analog modules across multiple generations of process design and applications.

ML architecture

The researchers said that we could program different machine learning architectures on ARYABHAT. Like digital processors, ARYABHAT can work well in a wide range of temperatures. They also noted that the architecture is "bias-scalable," meaning its performance stays the same even if the voltage or current changes. This architecture states the same chipset for either Internet of Things (IoT) applications that use very little energy or high-speed tasks like detecting objects.

The researchers have written about their findings in two pre-print studies, which their peers are now reviewing. The statement said they have also filed patents and plan to work with industry partners to bring the technology to market.

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